In recent years, SOI wafers have been used in device fabrication as semiconductor substrates having a multilayer film structure. For example, various devices, such as CPUs, logics, memories, physical sensors related to MEMS (Micro-Electro-Mechanical-Systems), biosensors, and RF devices, are fabricated by using SOI wafers.
As methods for fabricating the SOI wafers, wafer bonding methods and a SIMOX method are generally known. An ion implantation delamination method (also referred to as the SMART-CUT (a registered trademark) method), which is one of the wafer bonding methods, is proposed in Patent Document 1. In this method, an oxide film is formed on at least one of two silicon wafers, at least one of hydrogen ions and rare gas ions are implanted into a main surface of one of the wafers (a bond wafer) to form an ion-implanted layer in the interior of the wafer. The ion-implanted surface is then brought into close contact with a main surface of the other silicon wafer through the oxide film and the resultant wafer is then delaminated at the ion-implanted layer by performing a heat treatment at a temperature in the range of 300° C. to 600° C., or more than that. The ion implantation delamination method has an advantage in that an SOI wafer having a thin SOI layer with a film thickness uniformity of ±10 nm or less can be readily fabricated and an advantage in that the delaminated bond wafer can be reused several times to reduce cost.
On the other hand, in the SIMOX method, high concentration oxygen ions are implanted into the interior of a silicon wafer to form an oxygen ion-implanted layer, a buried oxide film (a BOX layer) is then formed in the silicon wafer by performing an annealing process at a high temperature of approximately 1300° C., and a layer of its surface side is used as the SOI layer.
A device pattern is then formed on the SOI wafer fabricated in the above manner. In this case, the feature size of pattern exhibits a wide range of pattern sizes from a relatively large size pattern for used in MEMS, RF devices and the like to a fine pattern for used in the latest CPUs, logics, memories and the like that have been significantly shrunken. Photolithography, which is one of the most important processes used for pattern formation in manufacture of various devices, has been used to form device patterns of various design rules.
In accordance with the feature size and so on, a wavelength from a visible light region to a deep ultraviolet light (DUV) region is used as the wavelength of an exposure light utilized for a photolithography operation. More specifically, the exposure light wavelength used herein is changed according to the design rules and so on. For example, in the case of formation of a relatively large size pattern such as the above mentioned MEMS, a mercury lamp having a wavelength of 436 nm or 365 nm is used. An excimer laser having a wavelength of 248 nm or 193 nm is used for the latest CPUs, logics, and memories, for example. It can be thought that an extreme ultraviolet light (EUV) having a wavelength of 13.5 nm will be used as the exposure light in future.
For the purpose of improving line width uniformity of an image of the pattern exposed to a light on the wafer, Patent Document 2 discloses an exposing device that is provided with a digital micro device as a reflection element array including a plurality of mirror elements that are each operable to control the reflection direction of an illumination light and controlling illumination distribution by adjusting reflection angles of the mirror elements separately from each other. Patent Document 2 also discloses use of an exposure light wavelength of 248 nm or 193 nm and use of the SOI wafer as a wafer subjected to photolithography.